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rev. 1.0 october 2010 www.aosmd.com page 1 of 16 AOZ1110 4a synchronous ezbuck regulator general description the AOZ1110qi is a high efficiency, easy to use, 4a synchronous buck regulator optimized for portable electronic devices. the AOZ1110qi works from a 2.7v to 5.5v input voltage range, and provides up to 4a of continuous output current with an output voltage adjustable down to 0.8v. with a 1% output accuracy rating, the AOZ1110 is designed for low tolerance applications, such as dsps and fpgas. the AOZ1110qi is available in a 24-pin 4x4 qfn package and is rated over a -40c to +85c ambient temperature range. features z 2.7v to 5.5v input voltage range z 30m high-side and 20m low-side mosfet z efficiency up to 95% z adjustable soft start z output voltage adjustable down to 0.8v z 4a continuous output current z selectable 500khz & 1mhz pwm operation z cycle-by-cycle current limit z over-voltage protection z short-circuit protection z thermal shutdown z power good indicator z small size 4x4 qfn-24 package applications z point of load dc/dc conversion for dsps, fpgas, asics and microprocessors z dvd and hdd z notebook pcs z telecom/networking/datacom equipment typical application figure 1. typical application vin vdd en fsel comp ss agnd pgnd pgood lx fb vin vout css = nc r c c c AOZ1110qi r3 r1 r2 c2, c3 22 f ceramic c1 22 f ceramic l1 mcu 1.0uh 5v
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 2 of 16 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/qualit y/rohs_compliant.jsp for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1110qi -40c to +85c 24-pin 4mm x 4mm qfn green product pin number pin name pin function 1 comp external loop compensation pin. 2 fb the fb pin is used to determine the output voltage via a resistor divider between the output and gnd. 3 en device enable pin, active high. 4 pgood power good signal output pin. it is an open drain logic output used to indicate the status of output voltages. connect a pull up resistor to vin. 5,6 nc no connect. 7 fsel frequency selection pin. tie this pin to ground, to set the switching frequency to 500khz; tie this pin to vdd, to set the switching frequency to 1mhz. 8, 23 agnd reference connection for controller ci rcuit. all agnd pins are connected internally. electrically needs to be connected to pgnd. also used as thermal connection for controller circuit. 9 vdd supply voltage to control circuit and gate drivers. connect a 10 ? resistor between vin and vdd and a 0.1 f capacitor from vdd to agnd to decouple noise voltage. 10, 11, 12 vin supply voltage input. all vin pins mu st be connected together externally. when vin voltage rises above the uvlo threshold the device starts up. 13, 14, 15, 16, 17, 18, 19, 20 lx pwm output connection to inductor. all lx pins must be connected together externally. also used as thermal connec tion for internal mosfet. 21, 22 pgnd power ground. all pgnd pins must be connected together. electrically needs to be connected to agnd. 24 ss soft start pin. connect a capacitor externally to control soft start period. leave it open for internal set soft-start time. 1 2 3 4 5 6 24 23 22 21 20 19 78 9101112 comp fb en pg nc nc 18 17 16 15 14 13 lx lx lx lx lx lx ss agnd pgnd pgnd lx lx fsel agnd vdd vin vin vin 24-pin 4mm x 4mm qfn (top view)
rev. 1.0 october 2010 www.aosmd.com page 3 of 16 AOZ1110 functional block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. recommended operating conditions the device is not guaranteed to operate beyond the maximum recommended operating conditions. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5k in series with 100pf. 2. the value of ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25c. the value in any given application depends on the user's specific board design. 500khz / 1 mhz oscillator agnd pgnd vin vdd en ss fb comp pgood lx otp ilimit pwm control logic uvlo & por softstart reference & bias 0.8v q1 q2 pwm comp level shifter + fet driver isen eamp + ? + ? + ? + pgood logic fesl parameter rating supply voltage (v in )6 v supply voltage (v dd )6 v lx to gnd -0.7v to 6v en to gnd -0.3v to 6v fb to gnd -0.3v to 6v comp to gnd -0.3v to 6v ss to gnd -0.3v to 6v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2kv pgood -0.3v to 6v fsel -0.3v to 6v nc -0.3v to 6v parameter rating supply voltage (v in ) 2.7v to 5.5v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package therma l resistance (2) 4x4 qfn-24 ( ja ) 45c/w
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 4 of 16 electrical characteristics t a = 25c, v in = v en = 3.3v, unless otherwise specified (3) symbol parameter condition min. typ. max. units v in supply voltage 2.7 5.5 v v uvlo input under-voltage lockout threshold v in rising v in falling 2.20 2.50 2.30 2.60 v v i in supply current (quiescent) v fb = 1.0v, l disconnected 1.5 3 ma i off shutdown supply current v en = 0v, active pgood = 100k excluding pg current 1 a v fb feedback voltage t a = 25c t a = -40c to 85c 0.792 0.784 0.800 0.800 0.808 0.816 v load regulation 0a < iload < 3a, v in = 3.3v, v out =1 .5v 0.2 % line regulation 2.7v < v in < 5.5v, v out = 1.5v iload = 100ma 0.2 % i fb fb input current 200 na enable v en en input threshold off threshold on threshold 1.2 0.4 v v v hys en input hysteresis 200 mv oscillator f o frequency f sel = vdd 0.85 1.0 1.15 mhz f sel = gnd 425 500 575 khz d max maximum duty cycle (4) 100 % t on_min minimum controllable on time (4) 200 ns error amplifier g vea error amplifier open loop voltage gain (4) 60 db g ea error amplifier transconductance (4) 200 a / v over current, over voltage and over temperature i lim current limit v in = 3.3v 5 6 7 a current limit response time (4) 200 ns t lo short circuit latch off time v fb = 0v 2 ms ovp over voltage protection 115 % ovp hyteresis 3 % over-temperature shutdown limit t j rising t j falling 150 100 c c oscillator i ss_out soft start pin source current ss = 0v, c ss = 0.001 f to 0.1 f 1.5 2.0 3.0 a i ss_in soft start pin sink current v in = 2.7v, c ss = 0.001 f to 0.1 f 1.5 3.0 5.0 ma t ss internal soft time c ss = open 500 s
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 5 of 16 notes: 3. specification in bold indicate an ambient temperature range of -40c to + 85c. these specifications are guaranteed by design. 4. guaranteed by design. pwm output stage r ds(on) high-side pfet on-resistance v in = 5v 33 64 m high-side pfet leakage v en = 0v, v lx = 0v 10 a r ds(on) low-side nfet on-resistance v lx = 5v 19 30 m low-side nfet leakage v en = 0v 10 a power good v olpg pg low voltage i (sink) = 1.0ma 0.3 v pg leakage current v = 5.5v 1 a pg upper threshold voltage fraction of set point 110 115 120 % pg lower threshold voltage fraction of set point 80 85 90 % pg hysteresis voltage 3 % t pg pg falling edge deglitch time 120 s symbol parameter condition min. typ. max. units electrical characteristics (continued) t a = 25c, v in = v en = 3.3v, unless otherwise specified (3)
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 6 of 16 typical performance characteristics circuit of figure 1 with internal soft-start. t a = 25c, v in = v en = 3.3v, v out = 1.2v unless otherwise specified. switching waveforms at light load switching waveforms at heavy load vo ripple 10mv/div vin ripple 0.1v/div vlx 5v/div il 1a/div enable 5v/div pgood 2v/div vo 0.5v/div iin 2a/div lx 5v/div pgood 2v/div vo 1v/div il 5a/div vo 50mv/div io 2a/div lx 5v/div pgood 2v/div vo 1v/div il 5a/div vo ripple 10mv/div vin ripple 0.1v/div vlx 5v/div il 1a/div start up waveforms short-circuit protection waveforms load transient waveforms short-circuit recovery waveforms 400ns/div 400ns/div 200us/div 1ms/div 1ms/div 1ms/div
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 7 of 16 efficiency efficiency (f sw = 1mhz, v in = 5v) vs. load current 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) efficieny (%) efficiency (f sw = 1mhz, v in = 3.3v) vs. load current 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) efficieny (%) output: efficiency (f sw = 500khz, v in = 5v) vs. load current 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) efficieny (%) efficiency (f sw = 500khz, v in = 3.3v) vs. load current 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 load current (a) efficieny (%) 3.3v 1.8v 1.2v output: 3.3v 1.8v 1.2v output: 1.8v 1.2v output: 1.8v 1.2v
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 8 of 16 detailed description the AOZ1110qi is a current-mode synchronous step down regulator with complimentary mosfet switches. the operating input voltage range is 2.7v to 5.5v. the output range can be adjusted to a minimum of 0.8v and supplies up to 4a of continuous current. features include cycle-by-cycle current limiti ng, short circuit protection, adjustable soft start and a power good output signal. enable and soft start the AOZ1110qi has both internal and external soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 2.5v and voltage on en pin is high. in the soft start, a 2 a internal current source charges the external capacitor at ss. as the ss capacitor is charged, the voltage at ss rises. the ss voltage clamps the reference voltage of the error amplifier, therefore output voltage rising time follows the ss pin voltage. with the slow ramping up output voltage, the inrush current can be prevented. if there is no external capacitor connected to the ss pin, the internal soft start will operate at 500 s. power good the output of power good is an open drain n-mosfet, which supplies an active high power good stage. a pull- up resistor (r3) should c onnect this pin to a dc power trail with maximum voltage no higher than 6v. the AOZ1110qi monitors the fb voltage: when the fb pin voltage is lower than 85% of the target voltage or higher than 115% of the target voltage, n-mosfet turns on and the power good pin is pulle d low, which indicates the power is abnormal. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the AOZ1110qi integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the inte rnal low-side n-mosfet switch to output. the internal adaptive fet driver guarantees no turn on overlap of both high-side and low-side switch. comparing with regulators using freewheeling schottky diodes, the AOZ1110qi uses freewheeling n-mosfet to realize synchronous rectification. it greatly improves the converter efficiency and reduces power loss in the low-side switch. the AOZ1110qi uses a p-mosfet as the high-side switch. it saves the bootstr ap capacitor normally seen in a circuit which is using an n-mosfet switch. switching frequency the AOZ1110qi switching frequency can be selected by fsel pin. when the fsel lo gic is tied to vdd, the switching frequency will be 1.0 mhz. when the fsel logic is tied to gnd, the switching frequency will be 0.5 mhz. output voltage programming output voltage can be set by feeding back the output to the fb pin by using a resistor divider network. in the application circuit shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r1 with equation below. some standard value of r 1 , r 2 and most used output voltage values are listed in table 1. table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. vo (v) r 1 (k ) r s (k ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? =
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 9 of 16 since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper p-mosfet and inductor. protection features the AOZ1110qi has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current si gnal is also used for over current protection. since the AOZ1110qi employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0v and 2.2v internally. the peak inductor current is automatically limited cycle by cycle. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 2.5v, the converter starts operation. when input voltage falls below 2.3v, the converter will be shut down. output over voltage protection (ovp) the AOZ1110qi monitors the feedback voltage: when the feedback voltage is higher than 15% of set value, it immediately turns off p-mosfet cycle by cycle to protect the output voltage overshoot at fault condition. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down both high side p-mosfet and low side n-mosfet if the junction temperature exceeds 150oc. the regulator will restart automatically under the control of soft start circuit when the junction temperature decreases to 100oc. application information the basic AOZ1110qi application circuit is show in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of AOZ1110qi to maintain steady input voltage and filter out the pulsing inpu t current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if we let m equal the conversion ratio: the relation between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2. it can be seen that when v o is half of v in , c in is under the worst curren t stress. the worst current stress on c in is 0.5 x i o . figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application circuits, other low esr tantalum capacitor may also be used. when selecting cerami c capacitors, x5r or x7r type dielectric ceramic capa citors should be used for their better temperature and voltage characteristics. note that the ripple curr ent rating from capacitor manufactures are based on certain amount of life time. further de-rating may be necessary in practical design. v in i o fc in 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 10 of 16 inductor the inductor is used to supply constant current to output when it is driven by a swit ching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduc tion loss. usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor need to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacito r must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specification is another important factor for selecting the output capacitor. in a buck converter circuit, output ripple voltage is determined by inductor value, switching fr equency, output capacitor value and esr. it can be calculated by the equation below: where; c o is output capacitor value, and esr co is the equivalent series resistor of output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, output capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is hi gh, output capacitor could be overstressed. loop compensation the AOZ1110qi employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole can be calculated by: i l v o fl ---------- - 1 v o v in -------- - ? ?? ?? ?? = i lpeak i o i l 2 -------- += v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- ?? ?? = v o i l esr co = i co_rms i l 12 ---------- = f p 1 1 2 c o r l ---------------------------------- - =
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 11 of 16 the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter control loop transfer function to get desired gain and phase. several different types of compensation network can be used for the AOZ1110qi. for most cases, a series capacitor an d resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwid th control loop. in the AOZ1110qi, fb pin and comp pin are the inverting input and the output of internal error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and, c c is the compensation capacitor in figure1. the zero given by the external compensation network, capacitor c c and resistor r c , is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when designing the comp ensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. the strategy for choosing r c and cc is to set the cross over frequency with rc and set the compensator zero with c c . using selected crossover frequency, f c , to calculate r c : where; f c is desired crossover frequency. for best performance, f c is set to be about 1/10 of switching frequency, v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v; g cs is the current sense circuit transconductance, which is 10 a/v. the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected cross- over frequency. c c can is selected by: the equation above can also be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . f z 1 1 2 c o esr co ------------------------------------------------ = f p 2 g ea 2 c c g vea ------------------------------------------ - = f z 2 1 2 c c r c ----------------------------------- = r c f c v o v fb ---------- 2 c o g ea g cs ----------------------------- - = c c 1.5 2 r c f p 1 ---------------------------------- - = c c c o r l r c --------------------- =
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 12 of 16 thermal management and layout consideration in the AOZ1110qi buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacitors , to the vin pin, to the lx pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the low-side n-mosfet. current flows in the second loop when the low side n- mosfet is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is strongly recommended to connect input capacitor, output capacitor, and pgnd pin of the AOZ1110qi. in the AOZ1110qi buck regulator circuit, the major power dissipating components are the AOZ1110qi and the output inductor. the total power dissipation of converter circuit can be measured by input power minus output power: the power dissipation of inductor can be approximately calculated by output curr ent and dcr of inductor: the actual junction temperature can be calculated with power dissipation in the aoz1012d and thermal impedance from junction to ambient: the maximum junction temperature of AOZ1110qi is 150oc, which limits the maxi mum load current capability. the thermal performance of the AOZ1110qi is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the recommended environmental conditions. several layout tips are listed below for the best electric and thermal performance. 1. the lx pins are connected to internal p-mosfet and n-mosfet drains. they are low resistance thermal conduction path and most noisy switching node. connect a large copper plane to lx pin to help thermal dissipation. for full load (4a) application, also connect the lx pads to the bottom layer by thermal vias to enhance the thermal dissipation. 2. do not use thermal relief connection to the vin and the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipation. 3. input capacitor should be connected to the vin pin and the pgnd pin as close as possible. 4. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. 5. make the current trace from lx pins to l to co to the pgnd as short as possible. 6. pour copper plane on all unused board area and connect it to stable dc nodes, like vin, gnd or vout. 7. keep sensitive signal trace far away form the lx pins. p total_loss v in i in v o i o ? = p inductor_loss i o 2 r inductor 1.1 = t junction p total_loss p inductor_loss ? () ja =
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 13 of 16 package dimensions, qfn 4x4-24l 18 19 1 24 12 13 6 7 24 top view side view bottom view l2 l3 e1 e2 d1 l l1 (4x) d/2 d b a e e/2 2 index area (d/2xe/2) aaa c 2x 2x e a3 4 a a1 a3 seating plane c 24 x b cbbb m ab 3 e e/2 pin#1 dia r0.30 e/2 ccc c ddd c aaa c 1 6 19 18 13 12 7 l d1/2 d1 d1/2
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 14 of 16 package dimensions, qfn 4x4-24l (continued) recommended land pattern dimensions in millimeters 0.80 0.05 0.30 2.70 1.35 1.05 0.45 0.40 0.45 0.15 0.75 0.02 0.20 ref 0.25 4.00 bsc 2.60 4.00 bsc 1.25 0.95 0.50 bsc 0.40 0.30 0.35 0.05 0.15 0.10 0.10 0.08 0.70 0.00 0.20 2.50 1.15 0.85 0.35 0.20 0.25 --- a a1 a3 b d d1 e e1 e2 e l l1 l2 l3 aaa bbb ccc ddd unit: mm 0.30 symbols min. typ. max. dimensions in inches 0.031 0.002 0.012 0.106 0.053 0.041 0.018 0.016 0.018 0.006 0.030 0.001 0.008 ref. 0.010 0.157 bsc 0.102 0.157 bsc 0.049 0.037 0.020 bsc 0.016 0.012 0.014 0.002 0.006 0.004 0.004 0.003 0.028 0.000 0.008 0.098 0.045 0.033 0.014 0.008 0.010 --- a a1 a3 b d d1 e e1 e2 e l l1 l2 l3 aaa bbb ccc ddd symbols min. typ. max. 1.30 2.60 0.30 0.30 0.95 0.35 0.30 1.85 1.85 1.85 1.85 0.25 0.50 ref (20x) 0.50 0.05 1.25 2.60 0.25 x 45? 1.30 0.25
AOZ1110 rev. 1.0 october 2010 www.aosmd.com page 15 of 16 tape and reel di mensions, qfn 4x4-24l package qfn 4x4 (12 mm) a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 4.35 0.10 0.10 1.10 min. 1.50 1.50 +0.1/-0.0 0.3 12.0 0.10 1.75 0.05 5.50 0.10 8.00 0.10 4.00 0.05 2.00 0.05 0.30 r v m n g s w nm ? 79.0 ? 330.0 2.0 12.4 12 mm tape size vr sk 0.5 2.0 10.5 g ??? h w1 ? 13.0 0.5 17.0 h k w w1 reel size ? 330 unit: mm unit: mm 1.0 +2.0/-0.0 +2.6/-1.2 d1 p1 e1 e2 e p2 k0 t a0 p0 b0 d0 c l 0.2 0.10 4.35 carrier tape reel trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets leader/trailer and orientation feeding direction
rev. 1.0 october 2010 www.aosmd.com page 16 of 16 AOZ1110 as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provid ed in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this datasheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not authorized for use as critical components in life supp ort devices or systems. part marking part n umber code assembly lot code fab & assembly location year & w eek code z1110qi fay wlt AOZ1110qi (qfn 4 x 4)

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